VHDL for logic synthesis

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• bmitc · Dec 3, 2020 · Recommends

  …and Hanna - Effective Coding with VHDL: Principles and Best Practices by Ricardo Jasinski (I'm using this to sort through the various ways to do things in VHDL and have best practices in my code.) - VHDL for Logic Synthesis by Andrew Rushton - FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC by Pong Chu

  on “NandGame – Build a Computer from Scratch” ↗
• panpanna · Jul 24, 2020 · Recommends

  …intentions, not trying to start a fight... --- There are some minor issues with your code that shows you are probably a verilog/SV guy and not an experienced VHDL guy. Please read Andrew Rushtons "VHDL for Logic Synthesis". I also recommend you read on VHDLs 9-valued logic and why it was designed this way and how it differs from verilogs Bit.

  on “The History, Status, and Future of FPGAs” ↗